A gain boosting switch for S/H circuit using clock boosting and symmetrical techniques to decrease the effect of channel charge injection

A new gain boosting switch using for bottom-plate sampling in the S/H circuit that enables increasing the accuracy of S/H circuit is proposed. A new method using symmetry and clock boosting techniques to remove the asymmetrical channel charge injection is also presented. Implemented in a 0.18μm CMOS process, the switch achieves ±0.3mV deviation and 924ps delay when a 5MHz square wave is sampled at 100Ms/s. The equivalent resistance ranges 4.2Ω to 7.5Ω and entire switch consumes 1.9μW at 1.8V supply when a 45MHz rail-to-rail sine wave is sampled at 100Ms/s. Particularly test results show that this new switch could be used in 10 bit, 100Ms/s pipeline ADCs.