Optimizing the package design with electrical modeling and simulation

To meet the challenge of providing a high-performance packaging solution for the next generation PA-RISC microprocessors, a task was undertaken to investigate the electrical performance and routing as the basis of comparison of two different substrate technologies, i.e. alumina and glass ceramic. In this presentation, the simulated performance of an I/O bus will be discussed. Signal integrity will be investigated for both substrate technologies and the I/O power supply system modeling for the bus are also covered. As part of the signal integrity investigation, the impact of routing on cross-talk is first discussed. The methodology of using a culprit/victim common mode model is then reviewed. Based on SPICE simulation results in both frequency domain and time domain follow, with an emphasis on cross-talk between culprit and victim lines. It is shown that a glass ceramic substrate provides better electrical performance in terms of reduced crosstalk, lower attenuation and faster transmission speed. For the I/O bus power supply investigation, an in-house software tool was used to generate SPICE decks for power supply simulation. Here, the focus is given to capacitor placement and its impact on the dynamic response of the power supply system. It is shown that appropriate capacitance and placement reduces the resonance characteristics (i.e. Q) of the system and voltage droop in response to a step excitation. Finally, the impact of the time constant associated with the on-chip bypass capacitors will be shown to play an important role in the dynamic response of the power supply. In conclusion, it is shown that a good power supply design must consider the interactions of the package with the die and, most likely, printed wiring board designs