DocumentCode
3161766
Title
Design and packaging challenges for on-board cache subsystems using source synchronous 400 Mb/s interfaces
Author
Pham, Nam ; Cases, Moises ; Guertin, Dave
Author_Institution
eServer X Series, IBM Corp., Austin, TX, USA
fYear
2001
fDate
2001
Firstpage
123
Lastpage
127
Abstract
This paper describes circuit and packaging design challenges encountered while attempting to optimize the source synchronous timing equations for the system level interconnects using a 200 MHz double data rate (DDR) level 3 (L3) cache subsystem. Various solutions to these challenges are presented. The delay skew budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated delay skew control techniques
Keywords
cache storage; integrated circuit design; integrated circuit interconnections; microprocessor chips; packaging; 200 MHz; delay skew; design optimization; microprocessor circuit; noise margin; on-board DDR level 3 cache subsystem; packaging; source synchronous interface; system-level interconnect; timing allocation; Clocks; Crosstalk; DRAM chips; Delay; Design optimization; Equations; Integrated circuit interconnections; Microprocessors; Packaging; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2001. Proceedings., 51st
Conference_Location
Orlando, FL
ISSN
0569-5503
Print_ISBN
0-7803-7038-4
Type
conf
DOI
10.1109/ECTC.2001.927706
Filename
927706
Link To Document