DocumentCode
3163416
Title
/spl Delta/L Extraction Using Parasitic Bipolar Transistors
Author
Wilson, D. ; Walton, A.J. ; Robertson, J.M. ; Holwill, R.J.
Author_Institution
Univesity Of Edinburgh
fYear
1988
fDate
22-23 Feb. 1988
Firstpage
85
Lastpage
89
Keywords
Artificial intelligence; Bipolar transistors; CMOS process; Electrical resistance measurement; Geometry; Length measurement; Low voltage; Microelectronics; Semiconductor device modeling; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1988. ICMTS. Proceedings of the 1988 IEEE International Conference on
Conference_Location
Long Beach, CA, USA
Type
conf
DOI
10.1109/ICMTS.1988.672940
Filename
672940
Link To Document