DocumentCode
3163722
Title
A 800 μA, 105 MHz CMOS crystal-oscillator digitally trimmable to 0.3 ppm
Author
Huang, Qiuting ; Basedau, Philipp
Author_Institution
Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
fYear
1996
fDate
23-27 Sep 1996
Firstpage
283
Lastpage
286
Abstract
A 105 MHz crystal oscillator consuming 800 μA at 1.7 V supply is described. The oscillator is part of a regulated system in a wireless device where the oscillation frequency is controlled digitally. This digital trimming of oscillation frequency is realized by binary capacitor banks of 10-bit resolution. The oscillator can be pulled from ±35 ppm to the required frequency with 0.3 ppm accuracy. The circuit has been fabricated in a 1 μm CMOS technology. The measured phase noise is -100 dBc/Hz at 100 Hz offset
Keywords
CMOS analogue integrated circuits; circuit tuning; crystal oscillators; digital control; frequency control; variable-frequency oscillators; 1 micron; 1.7 V; 105 MHz; 800 muA; CMOS crystal-oscillator; binary capacitor banks; digital trimming; oscillation frequency control; phase noise; CMOS technology; Capacitors; Circuits; Control systems; Digital control; Frequency; Noise measurement; Oscillators; Phase measurement; Phase noise;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location
Rochester, NY
ISSN
1063-0988
Print_ISBN
0-7803-3302-0
Type
conf
DOI
10.1109/ASIC.1996.552011
Filename
552011
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