A Single-Slope Look-Ahead Ramp (SSLAR) ADC for Column Parallel CMOS Image Sensors

A new analog-to-digital converter (ADC) algorithm was proposed for column-parallel CMOS image sensors. The proposed algorithm uses single-slope ramp ADC timing on a column-parallel CMOS image sensor. Single-slope look-ahead ramp (SSLAR) ADC algorithm introduces code hopping, fall back, and look-ahead operations considering statistical distribution of the sampled row of information on column sample and hold circuits. The algorithm was run on a number of standard images for performance comparison. It was also run on 300 random images to get speed and jump step trends. It was determined that the algorithm results in increased ADC speed; improving frame rate of the CMOS image sensor without degrading image quality. The new ADC provides 1.7times to 3.5times ADC speed improvement with less than 1.0% image quality degradation which a normal human eye cannot detect. Algorithm trades ADC speed and power consumption with image quality. The proposed algorithm shortens ADC conversion time resulting in reduced power consumption and increased frame rate of the column-parallel CMOS image sensor.