DocumentCode
3164304
Title
High performance data-path synthesis via communication metrics
Author
Seawright, Andrew ; Brewer, Forrest
Author_Institution
California Univ., Santa Barbara, CA, USA
fYear
1992
fDate
28-29 Feb 1992
Firstpage
60
Lastpage
67
Abstract
The authors present a novel decomposition of the high-level data-path synthesis problem taking as input scheduled procedural behavior and outputting geometrically placed and optimized linear data-paths. The technique uses communication based analysis to allow simultaneous synthesis of the placement, bindings, and RTL topology for high performance linear data-paths. In effect, the procedure creates an architecture and a layout with specified performance and cost constraints
Keywords
circuit layout CAD; RTL topology; architecture; bindings; communication based analysis; communication metrics; cost constraints; high performance data-path synthesis; high-level data-path synthesis; layout; optimized linear data-paths; performance constraints; placement; scheduled procedural behavior; simultaneous synthesis; Circuit synthesis; Circuit topology; Computer architecture; Costs; Degradation; Integrated circuit interconnections; Performance analysis; Routing; Scheduling; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-2610-0
Type
conf
DOI
10.1109/GLSV.1992.218364
Filename
218364
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