DocumentCode
3166816
Title
Session #2 Planar SOI device
Author
Doris, Bruce ; Fung, Samuel
Author_Institution
IBM, USA
fYear
2008
fDate
6-9 Oct. 2008
Firstpage
13
Lastpage
14
Keywords
CMOS process; CMOS technology; MOSFET circuits; Manufacturing processes; Parasitic capacitance; Power MOSFET; Research and development; Semiconductor device manufacture; Stress; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2008. SOI. IEEE International
Conference_Location
New Paltz, NY
ISSN
1078-621X
Print_ISBN
978-1-4244-1954-8
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2008.4656271
Filename
4656271
Link To Document