DocumentCode
3168297
Title
Delay balanced multipliers for low power/low voltage DSP core
Author
Sakuta, T. ; Wai Lee ; Balsara, P.T.
Author_Institution
Integrated Syst. Lab., Texas Instrum. Inc., Dallas, TX, USA
fYear
1995
fDate
9-11 Oct. 1995
Firstpage
36
Lastpage
37
Abstract
A simple but effective technique, which synchronizes the propagation of signals at each full adder stage, has cut the power dissipation of an array multiplier down to equal to or less than that of a Wallace-tree multiplier with a minimal penalty in performance and layout area. This delay balanced array multiplier is a strong candidate for low power and small area DSP core for portable equipment.
Keywords
delays; digital arithmetic; digital signal processing chips; integrated logic circuits; multiplying circuits; parallel processing; synchronisation; array multiplier; delay balanced multipliers; full adder stage; low power DSP core; low voltage DSP core; power dissipation reduction; Adders; Circuit simulation; Clocks; Delay; Digital signal processing; Laboratories; Low voltage; Power dissipation; SPICE; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Low Power Electronics, 1995., IEEE Symposium on
Conference_Location
San Jose, CA, USA
Print_ISBN
0-7803-3036-6
Type
conf
DOI
10.1109/LPE.1995.482454
Filename
482454
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