• DocumentCode
    3170290
  • Title

    A 100 mW 10 bit 100 MS/s all CMOS ADC

  • Author

    Hall, J.H. ; Nairn, D.G.

  • fYear
    1999
  • fDate
    1999
  • Firstpage
    5
  • Lastpage
    8
  • Abstract
    A l0-bit 100 MS/s ADC based on a pipelined architecture has been design for fabrication in a 0.35 um CMOS process. The complete converter includes an on-chip reference, an input buffer and sample-and-hold. The ADC core operates from a 2.7 V to 3.3 V supply and dissipates 93 mW when operated with a 3 V supply
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Advanced A/D and D/A Conversion Techniques and Their Applications, 1999. Third International Conference on (Conf. Publ. No. 466)
  • Conference_Location
    Glasgow
  • ISSN
    0537-9989
  • Print_ISBN
    0-85296-718-7
  • Type

    conf

  • DOI
    10.1049/cp:19990450
  • Filename
    793951
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3170290