Optimization strategy for the control ROM design

Microprogramming is used in VLIW processors and CISC processors. In the design of microprogrammed processors, to reduce the required microcode ROM area is performance-critical. In this paper, a novel method that can reduce the depth of microcode ROM is proposed. This method includes the design of addressing-entry and function-entry for each instruction. Meanwhile, with the aid of paged memory management concept, the design of a paged microcode memory that can reduce the microcode width is also proposed. Combined with these two methods, the area of the microcode memory can be effectively reduced with little expense of CPU frequency.