Physical and technological challenges of nanoelectronics devices for the end of the roadmap and beyond

The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power and high performance. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to implement for power consumption and low supply voltage management. Multigate architectures increase MOSFETs drivability, reduce power, and allow new memory devices opportunities to develop future applications. By introducing new materials (HiK, Ge, III-V, carbon based materials like diamond, graphene and CNTs, molecules,...), Si based CMOS will be scaled beyond the ITRS as the system-on- chip platform.