High speed Manchester Carry chain with carry-skip capability

Author

Asha, J. ; Senthilkumar, Jawahar

Author_Institution

ECE Dept., Anna Univ., Chennai, India

fYear

2015

fDate

19-20 March 2015

Firstpage

1

Lastpage

7

Abstract

Design of adder is the most focused area in VLSI systems. In this paper, multi-output domino Manchester carry chain with carry-skip capability is proposed. In the proposed design, even and odd carries are computed independently by two parallel carry chains. Carry-skip capability is applied to the odd carry chain which reduces the worst case critical path delay. The circuits are designed and simulated using Cadence Virtuoso tool with CMOS 180nm TSMC technology and IBM 130nm technology in LT SPICE IV. The proposed 64-bit Double chain Manchester Carry chain with carry-skip Adder shows a delay reduction of 52% compared to the Double chain Manchester Carry chain. The proposed Double chain Manchester carry chain with Carry-skip logic allows the elimination of intermediate buffers, thus retaining its area.

Keywords

CMOS logic circuits; adders; logic design; parallel processing; CMOS TSMC technology; IBM technology; LT SPICE IV; adder design; carry skip capability; critical path delay; double chain Manchester carry chain; high speed Manchester Carry chain; multi output domino Manchester carry chain; parallel carry chains; size 130 nm; size 180 nm; word length 64 bit; Adders; CMOS integrated circuits; Computers; Delays; Logic gates; Propagation delay; Transistors; Carry Look-ahead Adder (CLA); Carry-skip logic; Manchester Carry Chain (MCC); multi-output Domino;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit, Power and Computing Technologies (ICCPCT), 2015 International Conference on

Conference_Location

Nagercoil

Type

conf

DOI

10.1109/ICCPCT.2015.7159396

Filename

7159396