Novel devices in ESD protection

ESD protection circuits are part of any electronic circuit to ensure robustness against electrical surges. The choice of the ESD protection concept strongly depends on the IO devices. The integration of devices like DeMOS for high voltage interfaces in system on chip applications and multigate FETs in advanced CMOS requires new process optimization strategies taking into account the high current behavior of these devices. The specific thermal behavior of fin structures and the base push out in DeMOS devices during an ESD event are found to be detrimental. However, by the presented process and design modifications the initially very low ESD robustness of < 0.1 mA/mum can be raised to levels which are compliant with IC design constraints.