SFF-8431 12.5Gbps channel return loss (RL) failure debug: Simulation and measurement validation

Author

Minhong Mi ; Aude, Arlo ; Jie Chen ; Murugan, Rajen

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2015

fDate

26-29 May 2015

Firstpage

523

Lastpage

528

Abstract

The process of troubleshooting a 12.5Gbps SFF-8431 channel return loss compliance failure is described in details. Excellent simulation to measurement correlation has been achieved after capturing a capacitive dip at the package/PCB interface (“phantom” capacitance) with package and board physical layout geometries merged into one single electromagnetic simulation. Source of the “phantom” capacitance is identified and explained. Design techniques to circumvent the “phantom” capacitance and their effectiveness are evaluated through simulation studies and measurements.

Keywords

capacitance; failure analysis; modules; printed circuits; PCB interface; RL failure debug; SFF-8431; board physical layout geometry; capacitive dip; channel return loss; electromagnetic simulation; measurement correlation; measurement validation; package interface; phantom capacitance; printed circuit board; small form-factor pluggable module; Capacitance; Data models; Integrated circuit modeling; Loss measurement; Phantoms; Solid modeling; Temperature measurement; CPRI; SFF-8431; TDR; return loss;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th

Conference_Location

San Diego, CA

Type

conf

DOI

10.1109/ECTC.2015.7159640

Filename

7159640