DocumentCode
3176779
Title
Multi-clock Domain SoC Test Scheduling Based on Ant Colony Optimization Algorithm
Author
Shao, Jingbo ; Li, Yingmei ; Wang, Jianhua ; Huang, Yuyan ; Yu, Xiaodong
Author_Institution
Coll. of Comput. Sci. & Inf. Eng., Harbin Normal Univ., Harbin, China
fYear
2009
fDate
21-22 Dec. 2009
Firstpage
47
Lastpage
51
Abstract
This paper presents a variant test scheduling for multi-clock domain SoC. Test resources are allocated reasonably by using ant colony optimization, and test application time is minimized. Experimental results demonstrate that the proposed method improves test application time on previous methods.
Keywords
integrated circuit testing; optimisation; system-on-chip; ant colony optimization algorithm; multiclock domain SoC test scheduling; system-on-a-chip; Ant colony optimization; Application software; Automatic testing; Bandwidth; Circuit testing; Clocks; Educational institutions; Frequency; Processor scheduling; Scheduling algorithm; ant colony optimization; multi-clock domain; test scheduling;
fLanguage
English
Publisher
ieee
Conference_Titel
Internet Computing for Science and Engineering (ICICSE), 2009 Fourth International Conference on
Conference_Location
Harbin
Print_ISBN
978-1-4244-6754-9
Type
conf
DOI
10.1109/ICICSE.2009.45
Filename
5521635
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