An algorithm for parallel hardware accelerated switch level fault simulation

The complexity and large simulation time for switch level fault simulation has been addressed by performing two-dimensional parallel fault simulation using a parallel hardware accelerated fault simulator (PHAFS). The authors present an algorithm and complexity measure for parallel fault simulation as extended to the switch level. Using nine-valued logic, reverse level ordering, and the PHAFS, the switch level fault simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. This computational complexity is far less than that of traditional methods, since it is polynomial with respect to the number of reverse levels in the circuit as opposed to the number of devices in the circuit