Hardware implementation with off-line test capabilities of the RC6 block cipher

In 1997, the National Institute of Standards and Technology initiated a process to select a symmetric-key encryption algorithm to be used to protect sensitive federal information. In 1998 was announced the acceptance of fifteen candidate algorithms, and in 1999 six of them were selected. One of them is the RC6 cipher-block. In this paper we present a hardware implementation of this version of RC6 algorithm using VHDL (VHSIC Hardware Description Language). For this implementation we use Xilinx Foundation Series 1.5i software and VIRTEX XCV1000 board family. We chose this board for its characteristics: more than one million equivalent gates and 512 input/output buffers.