Efficient nanoscale VLSI standard cell library characterization using a novel delay model

Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanometer range VLSI circuits. Issues with NLDM based LUT are mostly due to the arbitrary choice of input signal transition time t_rin and load capacitance (C_l) and the large number of simulations to be performed for characterizing an entire standard cell library. In this paper, we present a systematic method to reduce standard cell library characterization time significantly. For this purpose we propose and use a simple and physically reasonable logic gate delay model in which delay varies linearly with C_l and t_rin. We also determine its region of validity in the (C_l, t_rin) space. We express the delay model coefficients and its region of validity as a function of inverter (or logic gate) size. We do not use device current/capacitance models in our work and hence the method is general enough to be used with scaling. With the help of this new model proposed, We were able to save approximately of 51% SPICE simulations during the standard cell library characterization. We observe that the delay obtained using our LUTs is as accurate as that of the delay obtained through traditional LUTs.