Measuring within-die spatial variation profile through power supply current measurements

Spatial variation in process parameters can have a significant impact on parametric yield of integrated circuits. We present a test structure and measurement technique for statistical characterization of process variation with programmable spatial granularity. The proposed structure can measure spatial variation at a desired level of granularity by controlling the leakage and on-current state in different spatial regions through input vectors and measuring the corresponding quiescent (I_DDQ) currents at power supply ports. This minimally invasive and low overhead variation measurement approach can be extended to measure spatial variation profiles in actual product chips by leveraging the existing power delivery architecture and power control circuits such as voltage islands and power gating. Measurements on a test chip fabricated in a 65 nm process show nearly a 100% leakage variation and 7% on-current variation over a 558 μm by 380 μm silicon area with nearly 3X chip-to-chip leakage variation.