Logical effort based automated transistor width optimization methodology

Author

Tiwari, Satish Chandra ; Gupta, Aneesh ; Singh, Kunwar ; Gupta, Maneesha

Author_Institution

N.S.I.T.(Univ. of Delhi), Delhi, India

fYear

2011

fDate

11-14 Dec. 2011

Firstpage

1067

Lastpage

1072

Abstract

The paper presents a new automated transistor width optimization methodology for SoC. The methodology is based on Logical Effort theory. The proposed methodology is completely automation based and uses different procedural blocks written in TCL (tool command language). The methodology requires SPICE netlist as input and optimizes transistor widths for minimum delay. Both sequential (flip-flop) and combinational (basic logic gates) logic blocks were optimized successfully using the proposed methodology.

Keywords

SPICE; authoring languages; circuit optimisation; flip-flops; logic circuits; logic gates; system-on-chip; transistor circuits; SPICE netlist; SoC; TCL; automated transistor width optimization methodology; basic logic gates; combinational logic blocks; flip-flop; logical effort theory; minimum delay; procedural blocks; sequential logic blocks; tool command language; transistor widths; Algorithm design and analysis; Delay; Flip-flops; Inverters; Logic gates; Optimization; Transistors; Flip-Flop; Logic Effort; VLSI; low power; optimization;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Communication Technologies (WICT), 2011 World Congress on

Conference_Location

Mumbai

Print_ISBN

978-1-4673-0127-5

Type

conf

DOI

10.1109/WICT.2011.6141396

Filename

6141396