A Test Wrapper Architecture for Hierarchical Cores

Modern system-on-a-chip SOC contains hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores is necessary to facilitate modular testing of SOC. In most of the prior work on wrapper design for embedded cores, all the cores are assumed to have a flattened hierarchy, it´s not suitable for real-life SOCs. In this paper, a generic IEEE 1500-compliant wrapper architecture for hierarchical cores is presented. Unlike prior wrapper design methods that assume a single flattened mode for hierarchical core wrappers, the reconfigurable wrapper presented for hierarchical cores that can operate efficiently in all the test modes, and can be directly applicable to real-life SOCs and support for multiple levels of hierarchical cores. A procedure is also proposed to get the TAM BUS width reduced without increasing testing time. Experimental results have proved that the TAM BUS width can get reduced 45% at most compare to flattened mode.