An efficient implementation of in-loop deblocking filters for H.264 using VLIW architecture and predication

Author

Dang, Philip P.

Author_Institution

STMicroelectronics Inc., San Diego, CA, USA

fYear

2005

fDate

8-12 Jan. 2005

Firstpage

291

Lastpage

292

Abstract

This work presents an efficient architecture to implement the in-loop deblocking filter for the H.264 video compression standard. The proposed solution is based on the implementation of a very long instruction word (VLIW) architecture, pipelined processing and predication technique.

Keywords

adaptive filters; code standards; data compression; parallel architectures; pipeline processing; video coding; H.264; VLIW architecture; in-loop deblocking filters; pipelined processing; predication; very long instruction word; video compression standard; Codecs; Decoding; Filtering; Filters; Hardware; MPEG 4 Standard; Quantization; Transform coding; VLIW; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2005. ICCE. 2005 Digest of Technical Papers. International Conference on

Print_ISBN

0-7803-8838-0

Type

conf

DOI

10.1109/ICCE.2005.1429832

Filename

1429832

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3184548