Fast matrix-multiplication algorithms on message-based systolic arrays

The author introduces a parallel structure termed a message-based systolic attached processor (MSAP) for the efficient implementation of matrix product algorithms. The architecture consists of a set of systolic nodes of fixed size and dimension connected by a global network, called the system interconnection network. The systolic nodes have their own local memory and can access a common global one. Communication protocols among the nodes are message-based and are similar to the ones used in the n-cube. The new architecture represents a family of algorithm-specific structures that can be custom-designed to solve a particular problem more efficiently. The author also describes a graph-theoretic technique for expressing the evolution of partial results in the structure as a function of the compute cycles in the form of a timing graph. Appropriate procedures for analyzing the timing graph are introduced. Analysis of the timing graph allows the modification of the array operation so that it could implement structured sparse matrix multiplication in reduced time