A Sigma-Delta Fractional-N Frequency Synthesizer Based on ADPLL

In this paper, we propose a fractional-N frequency synthesizer based on All Digital Phase Locked Loop (ADPLL). We use phase-frequency detector as PD, up/down counter as LF, P-Divider counter as DCO, and the dual-modulus N/N+1 divider is controlled by the output of the sigma-delta modulation to achieve the goal of spur reduction. The Sigma Delta Modulator (SDM) have noise-shaping characteristic though SDM will introduce inevitable quantization noise. We discuss the phase noise caused by the quantization noise brought by the Sigma-Delta noise-shaping technique.