Methodology of self-heating free parameter extraction and circuit simulation for SOI CMOS

Author

Nakayama, Hajime ; Su, Pin ; Hu, Chenming ; Nakamura, Motoaki ; Komatsu, Hiroshi ; Takeshita, Kaneyoshi ; Komatsu, Yasutoshi

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Sony Corp., Atsugi, Japan

fYear

2001

fDate

2001

Firstpage

381

Lastpage

384

Abstract

Novel SOI (Silicon On Insulator) model parameter extraction methodology based on the concept of SHE (Self-Heating Effect) free device modeling, is proposed and demonstrated for a 0.18 μm PD (Partially Depleted) SOI technology. In this methodology, prior to SPICE parameter extraction, the device thermal resistances are measured and the current loss due to SHE is added back analytically to DC I-V data. Therefore, the parameters are free from SHE. DC, AC, and transient simulation results using this technology show good agreement with measurement data

Keywords

CMOS integrated circuits; circuit simulation; integrated circuit modelling; silicon-on-insulator; thermal analysis; thermal resistance; transient analysis; 0.18 micron; DC I-V data; SOI CMOS; SOI model parameter extraction methodology; Si; circuit simulation; current loss; device thermal resistances; partially depleted SOI technology; self-heating effect free device modeling; self-heating free parameter extraction; Circuit simulation; Data mining; Electrical resistance measurement; Logic circuits; Parameter extraction; SPICE; Silicon on insulator technology; Temperature; Thermal conductivity; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 2001, IEEE Conference on.

Conference_Location

San Diego, CA

Print_ISBN

0-7803-6591-7

Type

conf

DOI

10.1109/CICC.2001.929805

Filename

929805