DocumentCode
3190944
Title
409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS
Author
Sun, Sheng ; Han, Yi ; Guo, Xinyu ; Chong, Kian Haur ; Mcmurchie, Larry ; Sechen, Carl
Author_Institution
Washington Univ., Seattle, WA, USA
fYear
2005
fDate
11-12 May 2005
Firstpage
52
Lastpage
58
Abstract
We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18μm process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone architecture and has 5 logic levels.
Keywords
CMOS integrated circuits; CMOS logic circuits; adders; delays; digital arithmetic; logic design; 0.18 micron; 64 bit; CMOS; OPL; TSMC; adder; inverter delays; output prediction logic; radix-3 Kogge-Stone architecture; Adders; CMOS logic circuits; Clocks; Delay; Fabrication; Microprocessors; Pulse inverters; Sun; Switches; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.2
Filename
1430110
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