• DocumentCode
    3191215
  • Title

    Hardware implementation of an additive bit-serial algorithm for the discrete logarithm modulo 2k

  • Author

    Li, L. ; Fit-Florea, Alex ; Thornton, M.A. ; Matula, D.W.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Southern Methodist Univ., Dallas, TX, USA
  • fYear
    2005
  • fDate
    11-12 May 2005
  • Firstpage
    130
  • Lastpage
    135
  • Abstract
    We describe the hardware implementation of a novel algorithm for computing the discrete logarithm modulo 2k. The circuit has a total latency of less than k table-lookup-determined shift-and-add modulo 2k operations. We introduce a one-to-one mapping between k-bit binary integers and k-bit encodings of a factorization of the integers employing the discrete logarithm. We compare the physical layout result for the circuit when k = 8, 16, 32, and 64.
  • Keywords
    circuit layout; floating point arithmetic; logic circuits; network analysis; additive bit-serial algorithm; circuit layout; discrete logarithm modulo 2k; integer factorization; k-bit binary integers; k-bit encodings; one-to-one mapping; table-lookup-determined shift-and-add modulo 2k operations; Circuits; Computer science; Contracts; Delay; Encoding; Floating-point arithmetic; Hardware; Pediatrics; USA Councils; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
  • Print_ISBN
    0-7695-2365-X
  • Type

    conf

  • DOI
    10.1109/ISVLSI.2005.35
  • Filename
    1430122
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3191215