Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

Author

Qin, Huifang ; Kumar, Animesh ; Ramchandran, Kannan ; Rabaey, Jan ; Ishwar, Prakash

Author_Institution

Univ. of California, Berkeley

fYear

2008

fDate

17-19 March 2008

Firstpage

30

Lastpage

34

Abstract

We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free V_DD to 155 mV. With a 100 mV noise margin, a 255 mV standby V_DD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V V_DD.

Keywords

SRAM chips; integrated circuit design; low-power electronics; optimisation; SRAM cell optimization techniques; SRAM leakage power; data retention voltage; error-tolerant SRAM design; size 90 nm; ultra-low power standby operation; voltage 1 V; voltage 100 mV; voltage 155 mV; voltage 255 mV; Circuits; Degradation; Design optimization; Error correction; Inverters; MOS devices; Random access memory; Semiconductor device measurement; Sleep; Voltage; DRV; ECC; SRAM; error tolerant; leakage; low power; low voltage; variation;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on

Conference_Location

San Jose, CA

Print_ISBN

978-0-7695-3117-5

Type

conf

DOI

10.1109/ISQED.2008.4479693

Filename

4479693