DocumentCode
3191769
Title
Evaluation of power gating structures focusing on power supply noise with measurement and simulation
Author
Takai, Yasumichi ; Hashimoto, Masanori ; Onoye, Takao
Author_Institution
Dept. Inf. Syst. Eng., Osaka Univ., Suita, Japan
fYear
2010
fDate
25-27 Oct. 2010
Firstpage
213
Lastpage
216
Abstract
This paper investigates the impact of power gating structure on power supply noise using 65nm test chip measurement and simulation. We focus on the body connection of power-gated circuits, and examine the contribution of a power-gated circuit as a decoupling capacitance during the sleep mode. Experimental results show that the well junction capacitance of the power-gated circuit with body-tied structure helps reduce power supply noise while a sharp drop cannot be mitigated due to its large RC time constant.
Keywords
integrated circuit measurement; integrated circuit noise; noise measurement; power supply circuits; body connection; decoupling capacitance; power gating structures; power supply noise; test chip measurement; Capacitance; Integrated circuit modeling; Logic gates; Noise; Noise measurement; Power supplies; Semiconductor device measurement; on-chip power supply noise; power gating; well structure;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conference on
Conference_Location
Austin, TX
Print_ISBN
978-1-4244-6865-2
Electronic_ISBN
978-1-4244-6866-9
Type
conf
DOI
10.1109/EPEPS.2010.5642585
Filename
5642585
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