Design of Low Power Double Edge Triggered D FF

This paper compares two previously published Double Edge Triggered D FlipFlops (DETDFF) with the proposed design for their performance and power consumption. For each DETDFF the optimal delay and power consumption are determined as the primary figure of merit. The DETDFF circuits designed by Gago and Wai Chung along with the proposed circuit were simulated using TSPICE for 0.13m technology CMOS process. The proposed design is shown to have the least delay and lowest power consumption with respect to other double edge triggered flip-flops.