DocumentCode
3192009
Title
RG-SRAM: a low gate leakage memory design
Author
Thondapu, Charan ; Elakkumanan, Praveen ; Sridhar, Ramalingam
Author_Institution
Dept. of Comput. Sci. & Eng., State Univ. of New York, Buffalo, NY, USA
fYear
2005
fDate
11-12 May 2005
Firstpage
295
Lastpage
296
Abstract
The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep sub-micron (VDSM) cache and embedded memories.
Keywords
SRAM chips; logic design; memory architecture; monolithic integrated circuits; PMOS pass transistors; RG-SRAM; VDSM cache; direct gate tunneling current; embedded memories; gate leakage dissipation; gate oxide thickness; low gate leakage memory design; off-state transistors; on-state transistors; reduced-gate SRAM; sub-70nm process technologies; Computer science; Gate leakage; Inverters; MOS devices; Random access memory; Subthreshold current; System-on-a-chip; Tunneling; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Print_ISBN
0-7695-2365-X
Type
conf
DOI
10.1109/ISVLSI.2005.64
Filename
1430161
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