Plasma induced damage testing methodology for the 0.13 μm CMOS technology

In this work, we investigate various testing methodologies for the evaluation of plasma induced damage to CMOS devices in the 0.13 μm technology. Results show that threshold voltage shift measurements of test structures with various antenna ratios at sub-20 Å gate oxide thickness are no longer a good indicator of plasma induced damage. Instead, gate leakage measurement techniques with and without voltage stress are more sensitive. This allows for the use of very simple two-terminal CMOS devices for plasma-induced damage evaluation. Furthermore, testing conditions for gate leakage current are investigated. The low voltage measurements showed the most sensitivity to plasma induced damage