A 10-b low-voltage CMOS pipelined analog-to-digital converter

A 10-b low-voltage CMOS pipelined analog-to-digital converter is described. A low-voltage technique is proposed for pipelined ADC that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. The cross-coupled configuration of multiplying digital-to-analog converter (MDAC) also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. Simulation results are given to demonstrate the potential advantage of the new technique.