An efficient 2n RNS scaler and its VLSI implementation

Scaling in Residue Number System (RNS) plays an important role in the application of RNS for Digital Signal Processing (DSP) systems. However, the scaling in RNS has been still regarded as a complex and time-consuming procedure. In this paper, we propose an efficient 2ⁿ scaling algorithm for RNS along with two relative propositions and their certifications based on Division Remainder Zero Theorem (DRZT). The 2ⁿ scaling is performed in only one step with the n LSBs of RNS integers. The VLSI implementation results show that the proposed scaler can obtain high performances in area, delay, and power consumption.