• DocumentCode
    3198052
  • Title

    A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip

  • Author

    Mariani, Giovanni ; Palermo, Gianluca ; Silvano, Cristina ; Zaccaria, Vittorio

  • Author_Institution
    ALaRI, Univ. of Lugano, Lugano, Switzerland
  • fYear
    2009
  • fDate
    27-28 July 2009
  • Firstpage
    21
  • Lastpage
    28
  • Abstract
    Application specific multi-processor systems-on-chip are currently designed by using platform-based synthesis techniques. In this approach, a wide range of platform parameters are tuned either at design-time or at run-time, to provide the best trade-offs in terms of the selected system figures of merit (such as power and throughput) for a dynamic application-specific workload. Among the design-time (hardware) configurable parameters we can find the memory sub-system configuration (e.g. cache size and associativity) and other architectural parameters such as the instruction-level parallelism of the system processors. Among the run-time (software) configurable parameters we can find the overall degree of task-level parallelism associated with each application running on the chip. Typically, while the design-time exploration is performed in the early development stages for a set of static parameters, the tuning of the run-time parameters is performed dynamically by a run-time management software module after the system has been deployed. In this paper, we introduce a methodology for identifying a hardware configuration which is robust with respect to the variable workload scenario introduced by the run-time management. Moreover, the proposed methodology is aimed at providing useful information about the optimal operating points of the applications in terms of task-level parallelism. The proposed methodology is based on the NSGA-II evolutionary heuristic algorithm assisted by an artificial neural network (ANN). We then introduce a run-time management policy capable to exploit the above information to maximize the performance of the system under power budget constraints. Experimental results show that the proposed technique is able to reduce the overall design space exploration time yet providing a near-optimal solution, in terms of hardware parameters, to enable an innovative and efficient run-time management policy.
  • Keywords
    evolutionary computation; integrated circuit design; microprocessor chips; neural nets; system-on-chip; NSGA-II evolutionary heuristic algorithm; application specific multiprocessor systems-on-chip; artificial neural network; design space exploration methodology; instruction level parallelism; memory subsystem configuration; platform-based synthesis techniques; run-time management software module; run-time resource management; task-level parallelism; Application software; Artificial neural networks; Design methodology; Hardware; Power system management; Resource management; Runtime; Software development management; Space exploration; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Specific Processors, 2009. SASP '09. IEEE 7th Symposium on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4244-4939-2
  • Electronic_ISBN
    978-1-4244-4938-5
  • Type

    conf

  • DOI
    10.1109/SASP.2009.5226331
  • Filename
    5226331