Parameterized Interconnect Modeling and Simulation in VLSI Design Considering Variations

This paper proposed a new algorithm for modeling and simulation of interconnect circuit in nanometer very large scale integration (VLSI) design considering manufacturing process variations. The approach is based on the existing passive reduced-order interconnect macromodeling algorithm (PRIMA). By satisfying the constraints of PRIMA, both macromodel stability and passivity are preserved, so that overall circuit stability is guaranteed for active driver and passive load interconnect circuits. As a result, transfer function of interconnect circuit under the influence of process variation is obtained, where reduction matrix is calculated once only for different values of parameters describing characteristics of process variations. Experiments demonstrate that result from proposed parameterized PRIMA considering process variation is very close to that obtained from PRIMA, while execution time is much less (up to 512X faster).