A Time and Storage Optimized Hardware Design for Context-Based Adaptive Binary Arithmetic Decoding in H.264/AVC

This paper proposes a hardware architecture for Context-based Adaptive Binary Arithmetic Code (CABAC) decoding in H.264/AVC. The proposed architecture takes both bin decoding efficiency and control efficiency into account. This architecture improves time and storage efficiency by taking full use of the new found characters of syntax elements (SEs). In this architecture, two controllers are designed to decode SEs. One is the main controller, and the other is the sub controller, which controls the decoding of residual block SEs. The parallel working mode of the two controller improves the time-consuming performance of the system. Experimental result shows that our design is quite rich for main profile CIF video stream at 30fps.