Soft error masking latch for sub-threshold voltage operation

Due to continuous technology scaling, the nodal capacitances reduction and power supply voltage lowering result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. CMOS circuits operating under sub-threshold voltage region are more susceptible than ever to externally induced radiation that is likely to bring about the occurrence of soft errors. Therefore, the robustness of the circuits against the soft errors is a requirement in nanoscale circuit designs. Since the previous soft error masking designs result in significant cost penalties in terms of power, area and performance when they applied to under V_th operation, the development of low-cost hardened designs for storage cells is important. In this paper, a novel radiation hardened latch is presented for high performance sub-threshold voltage operation. The critical charge is increased five times than that of the conventional latch with only 10% of area increment including 46% of power reduction. This result caused by shortening delay and reduced power loss arose from it.