Shift register based TPG for at-speed interconnect BIST

This article describes a novel approach to test pattern generation for at-speed interconnect built-in self-test. The novelty consists in both the original test sequence detecting opens, shorts and delays and the original design of the test pattern generator. The main idea is based on using a circular shift register and its proper initialization. Compared to other known techniques, Current approach provides the minimal hardware cost at the shortest test application time.