A fast-convergence and robust digital calibration algorithm for a 14-bit 200-MS/s hybrid pipelined-SAR ADC

This paper presents a fast-convergence and robust adaptive step size equalization approach for a 14-bit 200MS/s hybrid pipeline-SAR analog-to-digital converters (ADC). The proposed calibration approach corrects errors not only from capacitor mismatch, gain error, op amp nonlinearity, and comparator offset, but also the reference DAC error and inter-stage mismatch errors. It is robust and permits higher error margin for analog design. The proposed algorithm has been verified with gate level simulation as well as FPGA implementation, where the proposed design achieves a DNL of -0.59/0.28 LSB, an INL of -0.59/0.34 LSB and an SNDR of 84 dB at input near Nyquist frequency of 90.55MHz.