Cryogenic characterization of lateral DMOS transistors for lunar applications

The characterization and device physics study of a lateral DMOS transistor in the cryogenic regime (~ + 20 degC to - 180 degC) is presented in this paper. Normally, the characteristics of lateral MOSFETs improve with decreasing temperature. However, the asymmetrical nature of LDMOS devices, owing to the presence of a lightly doped drift region, causes the behavior to deviate from the expected characteristics at deep cryo temperatures. The output current is expected to increase with decreasing temperature, but our observations indicate that the current initially increases and then starts decreasing after a certain transition temperature. This is attributed to the carrier freeze-out phenomenon occurring in the drift region due to lower ionization energies available to the carriers. The paper will report results on the transfer and output characteristics of the JPL LDMOS devices as temperature decreases and attempt to explain the observation with physical reasoning.