NeuFlow: Dataflow vision processing system-on-a-chip

Author

Pham, Phi-Hung ; Jelaca, Darko ; Farabet, Clement ; Martini, Berin ; LeCun, Yann ; Culurciello, Eugenio

Author_Institution

Purdue Univ., West Lafayette, IN, USA

fYear

2012

fDate

5-8 Aug. 2012

Firstpage

1044

Lastpage

1047

Abstract

This paper presents a bio-inspired vision system-on-a-chip - neuFlow SoC implemented in the IBM 45 nm SOI process. The neuFlow SoC was designed to accelerate neural networks and other complex vision algorithms based on large numbers of convolutions and matrix-to-matrix operations. Post-layout characterization shows that the system delivers up to 320 GOPS with an average power consumption of 0.6 W. The power-efficiency and portability of this system is ideal for embedded vision-based devices, such as driver assistance, and robotic vision.

Keywords

computer vision; matrix algebra; neural nets; power consumption; silicon-on-insulator; system-on-chip; traffic engineering computing; 320 GOPS; IBM SOI process; NeuFlow SoC; complex vision algorithms; convolutions operations; dataflow vision processing system-on-a-chip; driver assistance; embedded vision-based devices; matrix-to-matrix operations; neural networks; portability; power 0.6 W; power consumption; power- efficiency; robotic vision; Computer architecture; Field programmable gate arrays; Machine vision; Roads; System-on-a-chip; Tiles; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2012 IEEE 55th International Midwest Symposium on

Conference_Location

Boise, ID

ISSN

1548-3746

Print_ISBN

978-1-4673-2526-4

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2012.6292202

Filename

6292202