Parallel phase accumulator architecture for DDFS

Author

Horowitz, Irwin ; La Rue, George S.

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA

fYear

2005

fDate

15-15 April 2005

Firstpage

63

Lastpage

66

Abstract

A parallel architecture is described for a phase accumulator (PA) in a direct digital frequency synthesizer (DDFS) intended for space-based applications. A comparison is made between the parallel and pipelined PA architectures in a 0.18 mum CMOS technology. The parallel architecture dissipates about 1/3 less power while achieving performance at least as high as the pipelined architecture. The accumulator designs are hardened against latch-up, total dose effects and single-event upsets through the use of guard rings, FET gate geometry and triple-mode redundancy (TMR) hardware

Keywords

CMOS digital integrated circuits; direct digital synthesis; parallel architectures; radiation hardening (electronics); 0.18 micron; CMOS technology; DDFS; FET gate geometry; direct digital frequency synthesizer; guard rings; latch-up effects; parallel phase accumulator; pipelined PA architectures; radiation hardness; single-event upsets; space-based applications; total dose effects; triple-mode redundancy hardware; Circuits; Clocks; Computer architecture; Frequency synthesizers; Parallel architectures; Pipeline processing; Power dissipation; Read only memory; Registers; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on

Conference_Location

Boise, ID

Print_ISBN

0-7803-9072-5

Type

conf

DOI

10.1109/WMED.2005.1431620

Filename

1431620