Double-gate SOI CMOS device DC & RF characterization

A variety of double gate (DG) MOSFET transistor structures are being developed to permit CMOS scaling to the sub-50nm regime. However, flexible dynamic threshold voltage control is urgently needed for ultralow power digital circuits, novel analog/RF circuits, and dynamically reconfigurable circuits. Independently double gated (IDG) FinFETs have recently been reported to have highly controllable Vt. However, a lithographically defined fin width of <10nm is required to achieve this. Other recently reported planar DG MOSFETs typically have oversized, non-self-aligned bottom gates and/or require epitaxial channel growth