DocumentCode
3210932
Title
Model-based guidelines to suppress cable discharge event (CDE) induced latchup in CMOS ICs
Author
Chatty, K. ; Cottrell, P. ; Gauthier, R. ; Muhammad, M. ; Stellari, Franco ; Weger, Alan ; Song, P. ; McManus, M.
Author_Institution
Semicond. Res. & Dev. Center, IBM Microeletronics, Essex Junction, VT, USA
fYear
2004
fDate
25-29 April 2004
Firstpage
130
Lastpage
134
Abstract
An analytical model has been developed to provide physical design guidelines to suppress CDE-induced latchup in CMOS ICs. The design guidelines implemented in two test chips in IBM´s 130nm technology successfully suppressed latchup against transient pulses of up to 6A peak current and against DC current pulses (EIA/JESD 78 test) of +/- 400mA.
Keywords
CMOS integrated circuits; flip-flops; integrated circuit modelling; integrated circuit reliability; 130 nm; 6 A; CMOS ICs; DC current pulses; Model-based guidelines; analytical model; physical design guidelines; suppress cable discharge event induced latchup; test chips; transient pulses; Analytical models; CMOS integrated circuits; CMOS technology; Circuit testing; Diodes; Guidelines; Inverters; MOSFETs; Semiconductor device modeling; Variable structure systems;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International
Print_ISBN
0-7803-8315-X
Type
conf
DOI
10.1109/RELPHY.2004.1315313
Filename
1315313
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