• DocumentCode
    3211713
  • Title

    Minimum verification test set for combinational circuit

  • Author

    Michinishi, Hiroyuki ; Yokohira, Tokumi ; Okamoto, Takuji

  • Author_Institution
    Fac. of Eng., Okayama Univ., Japan
  • fYear
    1992
  • fDate
    26-27 Nov 1992
  • Firstpage
    14
  • Lastpage
    19
  • Abstract
    A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2w elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2w elements for any CUT with up to four outputs is described
  • Keywords
    automatic testing; built-in self test; combinatorial circuits; logic testing; BIST; combinational circuit; minimum verification test set; redundancy; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Costs; Redundancy; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No.TH0458-0)
  • Conference_Location
    Hiroshima
  • Print_ISBN
    0-8186-2985-1
  • Type

    conf

  • DOI
    10.1109/ATS.1992.224428
  • Filename
    224428
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3211713