Packaging effect on reliability for Cu/low k structures

The packaging process can significantly increase the driving force for interfacial delamination and seriously impact the reliability of the low k chip. In this study we investigated the packaging effect due to die attach process where a high thermal load occurs during solder reflow before underfilling. With the high thermal load and without the underfill, the chip-package interaction is maximized and can be most detrimental to low k chip reliability. SiLK and MSQ are two low k dielectrics investigated in this paper to find the influence of low k properties on packaging reliability. In addition to different low k dielectrics, we investigated the effects due to the substrate material, die size and solder materials, including lead-free solder. The packaging effect was found to be more significant for flip-chip packages with lead-free solder than eutectic solder and high lead solder. Flip-chip packages with a ceramic substrate were found to have a smaller packaging effect than that with an organic substrate. Increasing the die size in a package increases the crack driving force for low k interfacial delamination, as expected. Packaging effect was smaller for the Cu/MSQ structure than the Cu/SiLK structure and the difference can be attributed to the higher Young´s modulus of the MSQ material.