Methodology for thermal aware topologies and partitioning with better lateral spreading

As the temperature became a first class design metric due to increased power densities, one of the key challenges in deep sub-micron technologies is to guarantee thermal safety while minimizing the performance impact. This highlights the need for thermal-aware physical design methodologies. In this paper we propose a practical methodology to improve lateral heat spreading by altering partitions and floorplan based on thermal hotspots obtained through dynamic simulations, at thermal design power conditions, without impacting timing and area. It also preserves the legacy and critical interfaces besides ensuring not to create new backend design issues - critical in case of proliferated designs. The experiments have been carried out using a complex mobile chipset.