M^{2}SI: An Improved Coherency Protocol in CMP

Now, most applications are need a CMP. But in CMP, the shared on-chip cache will cause data inconsistent. This paper proposes an improved coherency protocol in CMP: M²SI. This protocol contains four states. It takes full advantage of that all LIDs in CMP can exchange data at high speed. It is at the cost of that the Tags are multi-ports. All the processors´ level one data caches (LID) are linked on a ring bus. We then take a detailed comparison between this protocol and MES. Simulation results show that the M²SI protocol has an improvement about 30% comparing with MESI. Comparing with MID protocol, M²SI has only four stations and need only two bits to denote these states.